\nFrom some time I had in my mind The Fabulous Logic Analyzer<\/a> but parallel port is not what is available in modern laptops \ud83d\ude41
\nThen I saw how Saleae Logic16<\/a> works:-) It was impressive, especialy that it works also under Linux. But 100-200 euros are a little over my budget for new toy, so I started searching for affordable alternatives. After some digging on the Internet, I found that old Saleae Logic, CWAV USBee SX and other cheaper logic analyzers are based on Cypress CY7C68013A chip and have almost nothing more than this chip alone. So, I found on Ebay Lcsoft CY7C68013A Mini Board<\/em> prototyping board at less than $12 and now I have one \ud83d\ude42
\n
![\"LCSoft](\"https:\/\/majek.sh\/wp-content\/uploads\/2013\/02\/analyzer1-640x396.jpg\")
<\/a><\/p>\nIt’s not compatible with Saleae despite of programmed USB VID\/PID. But because I try to use opensource where possible, so my only choice was Sigrok<\/a>. It’s even better, because Lcsoft board has jumper to switch between ‘Saleae mode’ and ‘Cypress Development Kit’. Sigrok is quite new project, so gui is not it’s strong side, but at least there is possibility to sample and look at waveforms, and that’s all – even saving of sampled data is not available in gui \ud83d\ude41 On the contrary, command line sigrok_cli<\/strong> is quite powerful.<\/p>\n So, it’s time to analyze something, and standard video receiver which comes with Fox700 transmitter as bundle is ideal for it \ud83d\ude42 As you can see on the above pictures, I added simple level converters with resistors and Zener diodes. It’s because logic of video receiver is 5V and Cypress is 3.3V chip. Of course I tried without Zener diodes, but weird things were happening \ud83d\ude42<\/p>\n Sampling with sigrok_cli<\/strong>:<\/p>\n Ones and zeros are fine, but real power of Sigrok is ability to decode protocols:<\/p>\n Initial write and read are some junk, I think that chip used for programming tuner, had originally other purpose and peripherials, but what is really interesting is data written at address 0x61. So, let’s check what tuned frequency should be.<\/p>\n Divisor is 0x2b6c (MSB is transferred first) = 11116<\/p>\n According to datasheet, tuned frequency is: In this case synthesizer is tuned to 1389500000Hz = 1389.5MHz Success! \ud83d\ude42<\/p>\n One thing I’m missing in sigrok_cli<\/strong> is lack of timestamps (number of samples could be shown using -v flag), but it’s open source and everyone could add this (maybe even I) \ud83d\ude09<\/p>\n Right now, when I know how to control tuner in receiver, I could make my own controller. This time there will be a combined article – something about my new toy: logic analyzer, but also there will be introduction to diversity video receiver. Logic analyzer If you do anything with digital equipment or diy projects etc, logic …<\/span> Continue reading →<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[3,6,5],"tags":[24,11,48,47,46,49],"_links":{"self":[{"href":"https:\/\/majek.sh\/en\/wp-json\/wp\/v2\/posts\/770"}],"collection":[{"href":"https:\/\/majek.sh\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/majek.sh\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/majek.sh\/en\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/majek.sh\/en\/wp-json\/wp\/v2\/comments?post=770"}],"version-history":[{"count":46,"href":"https:\/\/majek.sh\/en\/wp-json\/wp\/v2\/posts\/770\/revisions"}],"predecessor-version":[{"id":1073,"href":"https:\/\/majek.sh\/en\/wp-json\/wp\/v2\/posts\/770\/revisions\/1073"}],"wp:attachment":[{"href":"https:\/\/majek.sh\/en\/wp-json\/wp\/v2\/media?parent=770"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/majek.sh\/en\/wp-json\/wp\/v2\/categories?post=770"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/majek.sh\/en\/wp-json\/wp\/v2\/tags?post=770"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\nAfter getting hard time to meet Sigrok dependency (Python3, sdcc and other unusual software), it compiled and started to run. Sigrok comes with it’s own firmware for Cypress chip, so no pirating here:-) <\/p>\n
\nIn Saleae compatible mode, Sigrok uploads standard firmware, so only 8 inputs are available at 24MHz sample rate.
\nBut when we switch to ‘native’ mode, we have logic analyzer with 16 inputs \ud83d\ude42 Of course 16 bit sampling is not available at 24MHz but when we narrow count of inputs up to 8, full sample rate is still available.<\/p>\n
\n![\"Sigrok's](\"https:\/\/majek.sh\/wp-content\/uploads\/2013\/02\/pulseview-640x417.png\")
<\/a><\/p>\nAnalyzing video receiver<\/h1>\n
\nI was wondering from some time what exactly happens on i2c bus, ie. how tuner is programmed for specific frequency, and an opportunity to get it known arrived \ud83d\ude42<\/p>\n![\"Standard](\"https:\/\/majek.sh\/wp-content\/uploads\/2013\/02\/video-receiver-640x480.jpg\")
<\/a>
\n![\"Logic](\"https:\/\/majek.sh\/wp-content\/uploads\/2013\/02\/analyzer2-622x480.jpg\")
<\/a><\/p>\n
\nlibsigrok 0.2.0
\nAcquisition with 8\/16 probes at 24 MHz
\n0:00000000 00000000 00000000 00000000
\n1:00000000 00000000 00000000 00000000
\n2:00000000 00000000 00000000 00000000
\n3:11111111 11111111 11111111 11111111
\n4:11111111 11111111 11111111 11111111
\n5:11111111 11111111 11111111 11111111
\n6:11111111 11111111 11111111 11111111
\n7:11111111 11111111 11111111 11111111<\/div><\/div>\n
\n$ sigrok-cli -i test.sr -a i2c:sda=0:scl=1
\ni2c: "START"
\ni2c: "ADDRESS WRITE" "0x68"
\ni2c: "ACK"
\ni2c: "DATA WRITE" "0x05"
\ni2c: "NACK"
\ni2c: "STOP"
\ni2c: "START"
\ni2c: "ADDRESS READ" "0x50"
\ni2c: "ACK"
\ni2c: "DATA READ" "0x00"
\ni2c: "NACK"
\ni2c: "STOP"
\ni2c: "START"
\ni2c: "ADDRESS WRITE" "0x61"
\ni2c: "ACK"
\ni2c: "DATA WRITE" "0x2b"
\ni2c: "ACK"
\ni2c: "DATA WRITE" "0x6c"
\ni2c: "ACK"
\ni2c: "DATA WRITE" "0x8e"
\ni2c: "ACK"
\ni2c: "DATA WRITE" "0xf0"
\ni2c: "ACK"
\ni2c: "STOP"<\/div><\/div>\n
\nAccording to documentation of SP5055 (synthesizer used on most tuners), 0x61 is it’s ‘always valid’ address, despite of signal on address settings pin, so it always works.
\nDuring that write there are 4 bytes transferred: 2 bytes of divider (unique for each selected channel), and 2 bytes for setting state of chip and external outputs (always the same).<\/p>\n
\nf = divisor * 16 * Fcomp<\/em>
\nFcomp is frequency of quarz or external generator (typically 4MHz) divided by 512, so:
\nf = divisor * 16 * 4000000 \/ 512<\/em><\/p>\n
\nBut that’s not the end – we must substract intermediate frequency 479.5MHz of tuner.
\nSo, in fact we are tuned to 910MHz and this is exactly a 0<\/strong> channel which was set on this receiver during test.<\/p>\n
\nWhy? Because documentation of SP5055 and some tuners shows that there is possibility to read also some data from tuner. Most interesting is little ADC connected typically to circuit that shows offset between set and receiving frequency. With this information it’s possible to automatically fine tune to exact frequency. It’s also possible to follow frequency change while transmitter warms up. And of course it’s possible to tune to any frequency in tuner range with 125kHz step \ud83d\ude09
\nTuning multiple tuners at once isn’t also a problem, so making simple diversity based on video rssi it’s also possible,
\n<\/p>","protected":false},"excerpt":{"rendered":"